Trench capacitors with one or more polysilicon electrodes for silicon integrated circuits may be fabricated using known methods, and have applications in structures such as DRAMs (Dynamic Random Access Memories) and analog circuits. Typically, the number of masking steps required depends on the number of polysilicon electrodes. For example, in forming a simple trench capacitor having one polysilicon electrode, in which the silicon substrate acts as the other electrode, a conventional known method includes steps of:
1. patterning and etching a trench in a silicon substrate;
2. formation of a capacitor dielectric on trench walls and bottom, typically silicon dioxide;
3. filling of the trench with polysilicon by a known method of chemical vapour deposition (CD) to provide the polysilicon electrode; and
4. planarization by removal of the surface substantially back to the level of the substrate surface.
The width of the trench polysilicon must be of such a dimension to allow a contact to be made by a method known in the industry. The resulting capacitor is formed between a deposited top polysilicon electrode and the silicon substrate. One masking step is required for patterning and etching the trench. Depending on the method of contact formation, another masking step may be required for defining a contact area to the substrate.
A known method for providing a capacitor having two polysilicon electrodes includes the steps of:
1. patterning and etching a trench in a silicon substrate;
2. forming an insulating dielectric layer on sidewalls and a bottom of the trench;
3. deposition and planarization of a first layer of polysilicon within the trench by a known method of CVD;
4. patterning and etching a second trench within the first polysilicon layer to form sidewalls of the first polysilicon layer in the trench to serve as one of the capacitor electrodes;
5. forming a layer of a capacitor dielectric on the etched first polysilicon layer;
6. filling the resulting dielectric lined trench inside the first polysilicon layer with a second polysilicon layer by a known method of CVD; and
7. planarization of the second polysilicon level with the substrate and first polysilicon surfaces.
Thus, a first masking step is required for defining the trench in the substrate (step 1) and a second masking step is required (step 4) for defining a second trench within the first polysilicon layer. The width of the second polysilicon within the second trench must be such as to allow a contact to be made by methods known in the industry. Depending on the method of contact formation, another masking step may be required for formation of a contact to the second polysilicon layer. Hence a minimum of two masking steps are required for formation of a trench linear capacitor with two polysilicon electrodes, one each for the trench and at least one polysilicon electrode.